This invention relates to a semiconductor device and, more particularly, to a semiconductor device with a high beak-down power semiconductor device.
A lateral DMOS field effect transistor, which has a drain electrode on the surface of a semiconductor substrate, is abbreviated as xe2x80x9cLDMOSxe2x80x9d transistor. The other surface area of the same p-type semiconductor substrate is available for other circuit components such as other kinds of semiconductor device or other LDMOS transistor electrically isolated from the LDMOS transistor. For this reason, the LDMOS transistor is popular to the semiconductor manufacturers as an output transistor of a power semiconductor integrated circuit device.
FIGS. 1A and 1B illustrate the prior art n-channel type LDMOS transistor. Reference numeral 301 designates a p-type silicon substrate. A lightly doped n-type impurity region 302 is grown on the major surface of the p-type silicon substrate 301. A field oxide layer 303 is selectively grown on the upper surface of the lightly doped n-type impurity region 302. A gate oxide layer 304 is further grown on the upper surface of the lightly doped n-type impurity region 302, and is contiguous to the field oxide layer 303. A gate electrode 305 is patterned on the gate oxide layer 304 and the field oxide layer 303. In other words, the gate electrode 305 is partially on the gate oxide layer 304 and partially on the field oxide layer 303. The field oxide layer 303 is patterned in such a manner that the lightly doped n-type impurity region 302 is exposed to a gap formed therein.
A p-type impurity region 306 is formed in the lightly doped n-type impurity region 302, and is located on both sides of the gap. The side surfaces of the gate electrode 305 on the gate oxide layer 304 are aligned with the p-n junction between the lightly doped n-type impurity region 302 and the p-type impurity region 306. The lightly doped n-type impurity region 302 penetrates into the lightly doped n-type impurity region 302 under the end portions of the gate electrode 305. A heavily doped p-type impurity region 311 is nested in the p-type impurity region 306, and a heavily doped n-type impurity region 312 is further formed in the p-type impurity region 306. The heavily doped n-type impurity region 312 and the heavily doped p-type impurity region 311 form a p-n junction in the p-type impurity region 306. A heavily doped n-type impurity region 313 is formed in the lightly doped n-type impurity region 302 in such a manner as to be exposed to the gap formed in the field oxide layer 303.
The lightly doped n-type impurity region 302, the p-type impurity region 306, the heavily doped n-type impurity region 312 and the heavily doped n-type impurity region 313 respectively serve as a drain region, a channel forming region, a source region and a drain contact region, which form parts of the prior art n-channel type LDMOS transistor.
The heavily doped n-type source region 312 is equal in depth to the heavily doped n-type drain contact region 313. The heavily doped p-type impurity region 311 is deeper than the heavily doped n-type source region 312, and is shallower than the lightly doped p-type channel forming region 306. The p-n junction between the p-type channel forming region 306 and the lightly doped n-type drain region 302 is shallower than the p-n junction between the lightly doped n-type drain region 302 and the p-type substrate 301. The field oxide layer 303 enhances the breakdown voltage of the drain region.
The heavily doped p-type impurity region 311 has a comb-like configuration, and the heavily doped n-type drain contact region 313 also has a comb-like configuration. The gate electrode 305 and the heavily doped n-type source region 312 are wound between the heavily doped p-type comb-like impurity region 311 and the heavily doped n-type comb-like drain contact region 313.
The prior art n-channel type LDMOS transistor is covered with an inter-layered insulating layer 321, and a source contact hole 323 and a drain contact hole 324 are formed in the inter-layered insulating layer 321. The heavily doped n-type source region 312 and the heavily doped p-type impurity region 311 are exposed to the source contact hole 323, and the heavily doped n-type drain contact region 313 is exposed to the drain contact hole 324. A source electrode 325 is formed on the inter-layered insulating layer 321, and passes through the source contact hole 323. The source electrode 325 is held in contact with the heavily doped n-type source region 312 and the heavily doped p-type impurity region 311. A drain electrode 326 is further patterned on the inter-layered insulating layer 321, and passes through the drain contact hole 324. The drain electrode 326 is held in contact with the heavily doped n-type drain contact region 313.
A problem is encountered in the prior art n-channel type LDMOS transistor in that a hot spot takes place. The hot spot is causative of serious damage to the prior art n-channel type LDMOS transistor. In detail, the heavily doped n-type source region 312 and the p-type impurity regions 306/311 form the p-n junction, and the p-type impurity region 306 and the lightly doped n-type drain region 302 form another p-n junction. These p-n junctions serve as an emitter-base junction and a base-collector junction, and the heavily doped n-type source region 312, the p-type impurity regions 306/311 and the lightly doped n-type drain region 302 behave as an emitter, a base and a collector of a parasitic n-p-n bipolar transistor. When excess voltage is applied to the drain electrode 326 due to surge or an inductance-load turn-off, strong electric field is produced in the depletion layer developed on both sides of the reversely biased p-n junction. Then, the avalanche break-down phenomenon takes place, and bread-down current Ibd flows. Moreover, the carriers flow out from the depletion layer around the reversely biased p-n junction as displacement current Idis. The total current Ibd and Idis passes through the surface of the lightly doped n-type drain region 302 and the p-type channel forming region 306, and flows into the source electrode 325. While the total current Ibd and Idis is flowing through the p-type channel forming region 306 against the resistance Rb, the potential level Vb in the p-type channel forming region 306 becomes higher than the potential level in the heavily doped n-type source region 312 by dVb=(Ibd+Idis)xc3x97Rb. Then, the p-n junction between the heavily doped n-type source region 312 and the p-type channel forming region 306 is forwardly biased, and the total current Ibd and Idis serves as base current in the parasitic n-p-n bipolar transistor. The parasitic n-p-n bipolar transistor turns on, and a large amount of collector current flows in the parasitic bipolar transistor. The collector current gives rise to increase of temperature. This results in reduction of the resistance, and the reduction of the resistance gives rise to further increase of the temperature. Thus, the parasitic n-p-n bipolar transistor is increased in temperature due to the positive feedback between the increase of the temperature and the reduction of the resistance. All the current is locally concentrated to the current path of the parasitic n-p-n bipolar transistor, and the hot spot takes place in the prior art n-channel type LDMOS transistor. Current due to the avalanche break-down is also locally concentrated, and gives rise to increase of the temperature.
The current path for the total current Ibd and Idis takes place in the p-type channel forming region 306 immediately under the heavily doped n-type source region 312. The p-type dopant impurity concentration in the current path is much lower than that of the remaining p-type channel forming region 306, because the p-type dopant impurity is compensated by the n-type dopant impurity in the heat treatment after introduction of the n-type dopant impurity for the heavily doped n-type source region 312. In other words, the dopant concentration in the current path is extremely low, and, accordingly, the resistance Rb is large in value. The larger the resistance Rb, the larger the increment of the potential level. Thus, the parasitic n-p-n bipolar transistor is liable to turn on, and the prior art n-channel type LDMOS transistor tends to be damaged. In an actual LDMOS transistor, the bipolar function locally takes place, and the LDMOS transistor is immediately damaged due to the rapid temperature rise before the positive feedback.
It is therefore an important object of the present invention to provide an LDMOS transistor, which is hardly damaged.
To accomplish the object, the present invention proposes to offer passages for breakdown current generated at a predetermined portion.
In accordance with one aspect of the present invention, there is provided a semiconductor device comprising a field effect transistor fabricated on a substrate, and the field effect transistor includes a drain layer formed on the substrate and doped with a first dopant impurity for imparting a first conductivity type thereto, a gate insulating layer formed on a first surface portion of the drain layer, a gate electrode formed on the gate insulating layer and having at least one gate portion elongated in a first direction, a drain contact region doped with the first dopant impurity heavier than the drain layer for imparting the first conductivity type thereto and having at least one drain contact sub-region formed in a second surface portion of the drain layer contiguous to one side of the first surface portion and elongated in the first direction, a channel forming region doped with a second dopant impurity for imparting a second conductivity type opposite to the first conductivity type thereto and formed in a third surface portion of the drain layer contiguous to the other side of the first surface portion and elongated in the first direction, an impurity region formed in the channel forming region and doped with the second dopant impurity heavier than the channel forming region, plural source regions doped with the first dopant impurity, formed in the channel forming region between the impurity region and the first surface portion in a self-aligned manner with the gate electrode and spaced from one another in the first direction, a drain electrode held in contact with the drain contact region and a source electrode held in contact with the plural source regions and the impurity region, wherein at least one of the drain contact region and the channel forming region has a deformed portion directed to the gap between the plural source regions, and the distance between the drain contact region and the channel forming region is measured in a second direction perpendicular to the first direction so as to be different between the deformed portion and a remaining portion of aforesaid at least one of the drain contact region and the channel forming region.